Intel CONTROLLERS 413808 - Manual (Page 693)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 693
I 2 C Bus Interface Units—Intel ® 413808 and 413812
The I
2
C interrupts are signalled through a single pin which provides a level sensitive
interrupt to the 4138xx interrupt control unit. The I
2
C Bus Interface Unit can cause and
interrupt when a buffer is full, buffer empty, slave address detected, arbitration lost, or
bus error condition occurs. All interrupt conditions must be cleared explicitly by
software. See Section 14.8.2, “I2C Status Register x — ISRx” on page 717 for details.
The I
2
C Data Buffer Register (IDBR) is an 8-bit data buffer that receives a byte of data
from the shift register interface of the I
2
C bus on one side and parallel data from the
4138xx internal bus on the other side. The serial shift register is not user accessible.
The control and status registers are located in the I
2
C memory-mapped address space
which ar eat offset (+2140H to +21BFH). The registers and their function are defined in
Section 14.8 .
The I
2
C Bus Interface Unit supports fast mode operation of 400 Kbits/sec. Fast mode
logic levels, formats, and capacitive loading, and protocols are exactly the same as the
100 Kbits/sec standard mode. Because the data setup and hold times differ between
the fast and standard mode, the I
2
C is designed to meet the slower, standard mode
requirements for these two specifications. Refer to the I
2
C Bus Specification for details.