Intel CONTROLLERS 413808 - Manual (Page 644)

Intel ® 413808 and 413812—SMBus Interface Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
644 Order Number: 317805-001US
12.3.1.2 Initialization Sequence
All Configuration and memory reads and writes are accomplished through an SMBus
write(s) and later followed by an SMBus read (for a read command). The SMBus write
sequence is used to initialize the following for the configuration access:
• Bus Number (Bus Number is ignored on 4138xx
• Device/Function (Device Number is ignored on 4138xx
• 12-bit Register Number (in 2 separate bytes on SMBus)
Each of the parameters above is sent on SMBus in separate bytes. The register number
parameter is initialized with two bytes and 4138xx ignores the most significant 4 bits of
the second byte that initializes the register number.
For memory reads and writes, the write sequence initializes:
• a 19-bit memory address offset (in 3 separate bytes on SMBus)
On 4138xx memory transactions allow access to the Peripheral Memory-Mapped
Registers only. All the Peripheral Memory-Mapped Registers on 4138xx are located in a
512-KByte contiguous memory space block that is relative to the PMMR Base Address
Register (PMMRBAR). Refer to the Peripheral Registers Chapter for more details on the
PMMRBAR register description. The 4138xx ignores the upper 5 bits of ADDR2 and the
entire ADDR3 fields when memory transaction is selected. For example, an internal bus
address is formed by concatenating the valid bits in the PMMRBAR and the 19 bits
obtained from the SMBus in the ADDR2, ADDR1, and ADDR0 fields. Refer to Table 431,
“SMBus Interface Registers for Memory Space Access” for the ADDRx fields.
The initialization of the information can be accomplished through any combination of
the supported SMBus write commands (Block, Word or Byte). The Internal Command
field for each write should specify the same internal command every time (read or
write). After all the information is set up, the last write (End bit is set) initiates an
internal read or write command. On an internal read when the data is not available
before the slave interface acknowledges this last write command (ACK), the slave does
a “clock stretch” until the data returns to the SMBus interface unit. On a internal write,
when the write is not complete before the slave interface acknowledges this last write
command (ACK), the slave “clock stretches” until the write completes internally. When
an error occurs (address error, target or master abort on the internal bus) during the
internal access, the last write command receives a NACK.