Intel CONTROLLERS 413808 - Manual (Page 790)

Intel ® 413808 and 413812—Test Logic Unit and Testability
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
790 Order Number: 317805-001US
18.2.3 TAP Controller Registers
The IEEE 1149.1 architecture specifies a minimum or two test data registers: bypass
and boundary scan. The IOP TAP controller extends this number to allow access to test
features within the device. Some registers are for public use, others are private. Per
the standard, each test data register has a fixed length and can be accessed using one
or more instructions. The 81348 design implements the following:
• Instruction Register
• Boundary Scan Register
• Bypass Register
• Device Identification Register
18.2.3.1 Instruction Register
Each of the TAP controllers in the design contain an instruction register (IR). Each IR is
a 7-bit, master/slave-configured, parallel-loadable, serial-shift register with latched
outputs. They are used in each unit to select the test data register to be accessed, the
test to be performed or both.
When the TAP controller is in the
Shift-IR state, instructions are loaded serially via
TDI clocked by the rising edge of TCK . The shifted-in instruction becomes active upon
latching from the serial-stages to the parallel-stages in the Update-IR state. At that
time the IR outputs, along with the TAP finite state machine outputs, are decoded to
select and control the test data register selected by that instruction. Upon latching, all
actions caused by any previous instructions must terminate.
On activation of
TRST# , the latched instruction asynchronously changes to the
IDCODE instruction. Additionally, upon entering the Test-Logic-Reset state, the
ID CODE instruction is latched and becomes active on the falling edge of TCK.
Because the TAP controllers are connected in series, each unit must receive its own
7-bit instruction during the Shift-IR state. The bypass instruction should be loaded into
the units that are not to be accessed. When the Intel XScale
®
Processor Core 1 TAP
controller is not MUXed into the TDI-TDO stream, the resulting instruction stream is
14-bits long. When the Intel XScale
®
Processor Core 1 TAP controller is inserted in the
stream, the instruction stream is 21-bits long.
For example, to load the TEST_REG_READ instruction into the TLUs IR when the Intel
XScale
®
Processor Core 1 TAP controller is not muxed into the TDI-TDO stream, the
data shifted into TDI during the Shift-IR state is:
As another example, to load the TEST_REG_READ instruction into the TLUs IR when
the Intel XScale
®
Processor Core 1 TAP controller is muxed into the TDI-TDO stream,
the data shifted into TDI during the Shift-IR state is:
0 1 0 0 0 0 1 1 1 1 1 1 1 1 - - - - - - > TDI
TEST_REG_READ BYPASS into
into TLU X-Scale core 0
0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - - -
>
TDI
TEST_REG_READ BYPASS into BYPASS into
into TLU X-Scale core 0 X-Scale core 1