Intel CONTROLLERS 413808 - Manual (Page 293)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 293
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.2 Internal Bus Addresses
All of the ATU registers are accessible through both inbound PCI configuration cycles
and the 4138xx core CPU (Register offsets 000H through 0FFH). T.
The location of these registers are specified as a relative offset to a 512KB aligned
global PMMR offset. The default for the 512KB aligned offset is 0 FFD8 0000H defined
by the PMMRBAR register. See also Chapter 19.0, “Peripheral Registers” .
The Internal Bus Address Offset to PMMRBAR of any ATU Register can be derived by
adding the 4 KB address aligned Internal Bus Memory Mapped Register Range Offset
( Table 140, “ATU Internal Bus Memory Mapped Register Range Offsets” on page 293 ) to
the Register Offset ( Table 141, “ATU PCI Configuration Register Space” on page 294 )
For example, when INTERFACE_SEL_PCIX# and CONTROLLER_ONLY# are both
asserted, the offset to PMMRBAR of the
“ATU Command Register - ATUCMD”
would be
(4 D000H+004H) or 4 D004H.
Note: The 4 KB Address Aligned Range Offset can be different depending on two configuration
straps as described in Table 140 .
Table 140. ATU Internal Bus Memory Mapped Register Range Offsets
INTERFACE_SEL_PCIX# CONTROLLER_ONLY#
Internal Bus MMR Address
Range Offset
(Relative to PMMRBAR)
Asserted (0) Asserted (0) +4 D000H
Asserted (0) Deasserted (1) +4 D000H
Deasserted (1) Asserted (0) +4 D000H
Deasserted (1) Deasserted (1) +4 8000H