Intel CONTROLLERS 413808 - Manual (Page 474)

Intel
®
413808 and 413812—SGPIO Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
474 Order Number: 317805-001US
6.6 Register Definitions
The SGPIO contains memory-mapped registers for:
• selecting ODx output signals that are driven on the serial data bus and to direct
LED pins,
• reading serial data from the input data bus,
• Programming Vendor Specific Code
Warning:
The SGPIO Units must be programmed for proper operation. By default the SGPIO units
are initialized to operate in SGPIO modes. The user must program the units to place
them in the desired mode of operations. The user must also select the start drive for
each SGPIO unit as the default start drive is drive number 0 for both SGPIO units.
Memory-Mapped Registers mentioned above are located as relative offsets of a 512 KB
aligned global PMMR Block. Default for the 512 KB aligned PMMR Block is
0 FFD8 0000H defined by the PMMRBAR register. See also Chapter 19.0, “Peripheral
Registers” .
Table 320. SGPIO Memory-Mapped Rejecters
Section, Register Name, Acronym, Page
Address Offsets
SGPIO Unit 0 SGPIO Unit 1
Table 321, “SGPIO Interface Control Register x - SGICRx” on
page 475
+2600H +2680H
Table 322, “SGPIO Programmable Blink Register x - SGPBRx” on
page 476
+2604H +2684H
Table 323, “SGPIO Start Drive Lower Register x — SGSDLRx” on
page 478
+2608H +2688H
Table 324, “SGPIO Start Drive Upper Register x — SGSDURx” on
page 480
+260CH +268CH
Table 325, “SGPIO Serial Input Data Lower Register x -
SGSIDLRx” on page 482
+2610H +2690H
Table 326, “SGPIO Serial Input Data Upper Register x -
SGSIDURx” on page 483
+2614H +2694H
Table 327, “SGPIO Vendor Specific Code Register x - SGVSCRx”
on page 483
+2618H +2698H
Reserved +261CH +269CH
Table 328, “SGPIO Output Data Select Register[0:7] x -
SGODSR[0:7]x” on page 484
+2620H through
+263FH
+26A0H through
+26BFH
Reserved
+2640H through
+267FH
+26C0H through
+26FFH