Intel CONTROLLERS 413808 - Manual (Page 546)

Intel
®
413808 and 413812—Peripheral Bus Interface Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
546 Order Number: 317805-001US
9.1 Overview
The Peripheral Bus Interface Unit (PBI) is a data communication path to the flash
memory components and peripherals of a 4138xx hardware system. The PBI allows the
processor to read and write data to these supported flash components and other
peripherals. To perform these tasks at high bandwidth, the PBI bus features a burst
read transfer capability which allows successive data transfers for multi-byte read
requests. The maximum PBI bus read burst size is four data transfers, regardless of
bus width. This means that some read requests made to the PBI may result in multiple
PBI bus burst accesses. For example a read request for 32 bytes on a 16-bit PBI bus
results in 4 bursts of four 16-bit words on the Peripheral Bus. Multi-byte read requests
and multi-byte write requests are supported differently by the PBI. Write requests are
limited to a maximum of 4 bytes only and must not span a DWORD boundary. The PBI
signals an address error when a write request has its byte-count out of range.
The peripheral bus is controlled by the on-chip bus masters: the Intel XScale
®
processor 0, the Intel XScale
®
processor 1, the ATU-E and the ATU-X units.
The address and data paths are demultiplexed, and the bus width is programmable to
8-, and 16-bit widths. The PBI performs the necessary packing and unpacking of bytes
to communicate properly across the 4138xx Internal Bus.
The PBI unit includes two chip enables. The PBI chip enables activate the appropriate
peripheral device when the address falls within one of the PBIs two programmable
address ranges. Both address ranges incorporate functionality that optimizes an
interface for Flash Memory devices. Each chip enable can support up to 32 MBytes of
addressability. For example, there are 25 address signals provided on the PBI interface.
Note: Be sure to refer to the System Software Architecture Specification and Design Guide for
details on supported Flash parts, since the Transport Firmware must provide support
for the Flash device in addition to PBI.