Intel CONTROLLERS 413808 - Manual (Page 616)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
616 Order Number: 317805-001US
10.7.23 FIQ Interrupt Source Register 2 — FINTSRC2
The FIQ Interrupt Source register 2 is a 32-bit Coprocessor 6 control register used to
specify which interrupts that are steered to the internal FIQ exception are unmasked by
the INTCTL2 register and active. The INTSTR2 control register is used to steer
individual interrupts to the FIQ exception.
The FINTSRC2 register may be used by an Interrupt Service Routine (ISR) to
determine quickly the source of an FIQ interrupt.
Table 405. FIQ Interrupt Source Register 2 — FINTSRC2
Bit Default Description
31 0
2
Reserved.
30 0
2
South Internal Bus Bridge Error Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL2
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL2
29:14 0
2
Reserved.
13 0
2
SRAM DMA Error
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL2
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL2
12 0
2
SRAM DMA Normal Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL2
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL2
11:03 0
2
Reserved.
02 0
2
Reserved.
01 0
2
Reserved.
00 0
2
Reserved.
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor
address
CP6, Page 7, Register 2