Intel CONTROLLERS 413808 - Manual (Page 547)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 547
Peripheral Bus Interface Unit—Intel
®
413808 and 413812
9.2 Peripheral Bus Signals
Bus signals consist of three groups:
• address
• data
• control/status
9.2.1 Address Signal Definitions
The address signal group A[24:0] consists of 25 lines which allows the PBI to address
up to 32 MBytes per peripheral device. During and address cycle (T
A
), the processor
drives A[24:0] with the starting address of the bus access. During bursted read access
the wait cycle (T
W
) and the T
D
cycle, A[2:0] address pins provide incrementing byte
addresses.
9.2.2 Data Signal Definitions
The data signal group D[15:0] consists of 16 lines. The PBI supports either an 8-bit
data bus width on D[7:0] or 16-bit data bus width on D[15:0] . During the address
cycle (T
A
), bits D[1:0] carry the SIZE of the access.
9.2.3 Control/Status Signal Definitions
The control/status signals control peripheral device enables and direction. All output
control/status signals are three-state.
A peripheral read may be either non-burst or burst. A non-burst read ends after one
data transfer to a single location.
When the data bus is configured for 16 bits, address bits
A[2:1] are used to burst
across up to four short-words. For an 8-bit data bus, address bits A[1:0] are used to
burst across up to four bytes.
The Output Enable,
POE# , is used for burst or non-burst read accesses to a peripheral
device and is asserted during the T
A/
T
W
/T
D
states.
The Write Enable, PWE# , is used for non-burst write accesses to a peripheral device
and is asserted during the T
W
/T
D
states.
The PBI Reset, PB_RSTOUT# , is used to reset the peripheral device. It has the same
timings as the internal bus reset signal.
Note: Burst write accesses are not supported by the PBI bus. A multi-byte write request
made to the PBI translates into multiple single data write transactions on the PBI bus.
For example, each write transaction on the PBI bus ends after one data transfer to a
single address location. Note that the number of single data write transactions initiated
on the PBI bus are dependent to the PBI bus width.