38 pci express vendor_defined message header, Intel, Bit default description – Intel CONTROLLERS 413808 User Manual

Page 384

Intel

413808 and 413812—Address Translation Unit (PCI Express)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

384

Order Number: 317805-001US

3.17.105 Inbound Vendor Message Header Register 0 - IVMHR0

The Inbound Vendor Message Header Registers capture the header for a vendor defined

message received on the PCI Express interface. Once the inbound message has been

processed, the Inbound Vendor Message Received bit is set in the

ATU Interrupt Status

. Subsequent inbound vendor messages are held in the inbound

posted queues until the status bit is cleared or the mask bit is set in the

ATU Interrupt

Mask Register - ATUIMR

. When the mask bit is set, then Vendor_Defined Type 0

messages are treated as unsupported requests and Vendor_Defined Type 1 messages

are silently discarded.
Vendor_Defined message format is shown below in

Figure 38

Table 245. Inbound Vendor Defined Message Header Register0 - IVMHR0

Bit

Default

Description

31:24

00H

Header Byte 0

23:16

00H

Header Byte 1

15:8

00H

Header Byte 2

7:0

00H

Header Byte 3

Figure 38. PCI Express Vendor_Defined Message Header

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Byte 0> R Fmt

x 1

Type

P Attr R

Length

Byte 4>

Requester ID

Tag

Message Code -

Vendor_Defined

Byte 8>

Bus Number

Device Num Fnc No

Vendor ID

Reserved

Byte 12>

(For Vendor Definition)

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+340H