2 gpio input data register - gpid, 2 gpio input data register — gpid, 479 gpio input data register — gpid – Intel CONTROLLERS 413808 User Manual

Page 726: Gpio, P_rst, Bus pins following the deassertion of, Intel, Bit default description, Gpio[15, Gpio[14

Intel

413808 and 413812—General Purpose I/O Unit

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

726

Order Number: 317805-001US

15.2.2

GPIO Input Data Register — GPID

The GPIO Input Data Register reflects the state of the appropriate

GPIO

bus pins

following the deassertion of

P_RST#

Table 479. GPIO Input Data Register — GPID (Sheet 1 of 2)

Bit

Default

Description

31:16

0000H

Reserved

GPIO[15]

during

P_RST#

assertion

GPIO15 Input Data — This bit reflects the state of the

GPIO[15]

pin.

GPIO[14]

during

P_RST#

assertion

GPIO14 Input Data — This bit reflects the state of the

GPIO[14]

pin.

GPIO[13]

during

P_RST#

assertion

GPIO13 Input Data — This bit reflects the state of the

GPIO[13]

pin.

GPIO[12]

during

P_RST#

assertion

GPIO12 Input Data — This bit reflects the state of the

GPIO[12]

pin.

GPIO[11]

during

P_RST#

assertion

GPIO11 Input Data — This bit reflects the state of the

GPIO[11]

pin.

GPIO[10]

during

P_RST#

assertion

GPIO10 Input Data — This bit reflects the state of the

GPIO[10]

pin.

GPIO[9]

during

P_RST#

assertion

GPIO9 Input Data — This bit reflects the state of the

GPIO[9]

pin.

GPIO[8]

during

P_RST#

assertion

GPIO8 Input Data — This bit reflects the state of the

GPIO[8]

pin.

GPIO[7]

during

P_RST#

assertion

GPIO7 Input Data — This bit reflects the state of the

GPIO[7]

pin.

GPIO[6]

during

P_RST#

assertion

GPIO6 Input Data — This bit reflects the state of the

GPIO[6]

pin.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale

processor Local Bus Address

offset

+2484H