Intel CONTROLLERS 413808 - Manual (Page 296)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
296 Order Number: 317805-001US
+134H Section 3.17.82, “Error Source Identification Register - RERR_ID” on page 364
+1E0H Section 3.17.83, “Device Serial Number Capability - DSN_CAP” on page 364
+1E4H Section 3.17.84, “Device Serial Number Lower DW Register - DSN_LDW” on page 365
+1E8H Section 3.17.85, “Device Serial Number Upper DW Register - DSN_UDW” on page 365
+1ECH Section 3.17.86, “PCI Express Advisory Error Control Register - PIE_AEC” on page 366
+1F0H Section 3.17.87, “Power Budgeting Enhanced Capability Header - PWRBGT_CAPID” on page 367
+1F4H Section 3.17.88, “Power Budgeting Data Select Register - PWRBGT_DSEL” on page 367
+1F8H Section 3.17.89, “Power Budgeting Data Register - PWRBGT_DATA” on page 368
+1FCH Section 3.17.90, “Power Budgeting Capability Register - PWRBGT_CAP” on page 369
+200H -
+25FH
Section 3.17.91, “Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23]” on page 370
+300H Section 3.17.92, “Outbound I/O Base Address Register - OIOBAR” on page 371
+304H Section 3.17.93, “Outbound I/O Window Translate Value Register - OIOWTVR” on page 372
+308H Section 3.17.94, “Outbound Upper Memory Window Base Address Register 0 - OUMBAR0” on page 373
+30CH Section 3.17.95, “Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0” on page 374
+310H Section 3.17.96, “Outbound Upper Memory Window Base Address Register 1 - OUMBAR1” on page 375
+314H Section 3.17.97, “Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1” on page 376
+318H Section 3.17.98, “Outbound Upper Memory Window Base Address Register 2 - OUMBAR2” on page 377
+31CH Section 3.17.99, “Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2” on page 378
+320H Section 3.17.100, “Outbound Upper Memory Window Base Address Register 3 - OUMBAR3” on page 379
+324H Section 3.17.101, “Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3” on page 380
+328H Reserved
+32CH Section 3.17.102, “Outbound Configuration Cycle Address Register - OCCAR” on page 381
+330H Section 3.17.103, “Outbound Configuration Cycle Data Register - OCCDR” on page 382
+334H Section 3.17.104, “Outbound Configuration Cycle Function Number - OCCFN” on page 383
+340H Section 3.17.105, “Inbound Vendor Message Header Register 0 - IVMHR0” on page 384
+344H Section 3.17.106, “Inbound Vendor Message Header Register 1 - IVMHR1” on page 385
+348H Section 3.17.107, “Inbound Vendor Message Header Register 2 - IVMHR2” on page 386
+34CH Section 3.17.108, “Inbound Vendor Message Header Register 3 - IVMHR3” on page 387
+350H Section 3.17.109, “Inbound Vendor Message Payload Register - IVMPR” on page 387
+360H Section 3.17.110, “Outbound Vendor Message Header Register 0 - OVMHR0” on page 388
+364H Section 3.17.111, “Outbound Vendor Message Header Register 1 - OVMHR1” on page 389
+368H Section 3.17.112, “Outbound Vendor Message Header Register 2 - OVMHR2” on page 390
+36CH Section 3.17.113, “Outbound Vendor Message Header Register 3 - OVMHR3” on page 390
+370H Section 3.17.114, “Outbound Vendor Message Payload Register - OVMPR” on page 391
+380H Section 3.17.115, “PCI Interface Error Control and Status Register - PIE_CSR” on page 392
+384H Section 3.17.116, “PCI Interface Error Status - PIE_STS” on page 393
+388H Section 3.17.117, “PCI Interface Error Mask - PIE_MSK” on page 394
+38CH Section 3.17.118, “PCI Interface Error Header Log - PIE_LOG0” on page 395
+390H Section 3.17.119, “PCI Interface Error Header Log 1 - PIE_LOG1” on page 395
+394H Section 3.17.120, “PCI Interface Error Header Log 2 - PIE_LOG2” on page 396
+398H Section 3.17.121, “PCI Interface Error Header Log - PIE_LOG3” on page 396
+39CH Section 3.17.122, “PCI Interface Error Descriptor Log” on page 397
+3B0H Section 3.17.123, “ATU Reset Control Register - ATURCR” on page 397
a. Refer to the Messaging Unit Chapter for MSI Register Definitions
b. Refer to the Messaging Unit Chapter for MSI-X Register Definitions.
Table 141. ATU PCI Configuration Register Space (Sheet 3 of 3)
Interna
l Bus
Address
Offset
ATU PCI Configuration Register Section, Name, Page