Intel CONTROLLERS 413808 - Manual (Page 434)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
434 Order Number: 317805-001US
4.7.25 Message Data Register- Message_Data
The value in the Message Data Register contains the data used during an MSI write
transaction. When two unique messages are enabled, one message is reserved for the
Outbound Post Queue Interrupt and the other message represents all of the Outbound
Doorbell and Outbound Message Interrupts. When only one message is enabled, all of
these interrupts are represented by a single message. Interrupt handler software needs
to read the 4138xx Outbound Interrupt Status Register to determine the cause of the
interrupt when more than one source is represented by a single message.
During an MSI write data phase, the value in the Message Data Register is driven on to
AD[15:0] while AD[31:16] are driven to zero. C/BE[3:0]# are asserted during the
data phase of the memory write transaction.
Note: Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 290. Message Data Register - Message_Data
Bit Default Description
15:00 0000H
Message Data - System software specifies a 16-bit value to be transferred during the data phase of an
MSI write transaction.
During initialization, system software can allocate two messages to the 4138xx by writing “001” to the
Multiple Message Enable field of the Message Control Register. In this case, the hardware shall modify
bit 0 of the Message Data value before generating the MSI write transaction.
The Host I/O Interface Outbound interrupts are distributed across the two messages by the setting and
clearing of bit 0 of the Message Data Register’s contents before the data is used for the MSI write:
0 = Outbound Post Queue Interrupt
1 = Outbound Doorbell and Outbound Message Interrupts
When software leaves the Multiple Message Enable field of the Message Control Register at its’ default
value of “000”, the 4138xx has only been allocated one message. Consequently, the value in the MSI
data register is transmitted unmodified during an MSI write cycle.
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
ACH
Internal Bus Address Offset
0ACH