Intel CONTROLLERS 413808 - Manual (Page 241)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 241
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.3.1.3 Inbound Memory Read Transaction
An inbound read transaction is initiated by a PCI Express requester and is targeted at
either 4138xx local memory or a 4138xx memory-mapped register space. The read
transaction is propagated through the inbound non posted queue (INPQ) and read data
is returned through outbound completion data and header queues (OCPLHQ, OCPLDQ).
In PCI Express, all read transactions are processed as split transactions. The ATUs PCI
Express interface accepts the read transaction and forwards the read request through
to the internal bus and returns the read data to the PCI Express Link. Data flow for an
inbound read transaction is summarized in the following statements:
• The ATU accepts the read transaction when the PCI address is within one of the
inbound translation windows defined by ATU Inbound Base Address Register,
Inbound Upper Base Address Register, and Inbound Limit Register.
• When the transaction crosses a 1KB aligned boundary it is fragmented into smaller
requests that do not cross the aligned boundary before it is issued on the internal
bus. Since PCI Express transactions cannot cross a 4KB boundary, a single read
request is broken into at most 4 1KB transactions.
• When sufficient space exists in OCPLDQ, request internal bus and issue request.
• Save the completion header information in the OCLUT.
• ATUE can handle a maximum of 4 outstanding internal bus requests at one time.
• All internal bus read requests result in split completions. The completion data is
queued in the Outbound Completion Data Queue.
• A zero length read (memory read request of 1 DW with no bytes enabled) has no
side-effects.
• Once a completion transaction has started, it continues until one of the following is
true:
— The length is satisfied.
— An internal bus Master Abort or Target Abort was detected. The ATU generates
a Completion TLP with a Completer Abort status to inform the requester about
the abnormal condition. The INPHQ for this transaction is flushed. Refer to
Section 3.9.3 .
The data flow for an inbound read transaction on the internal bus is summarized in the
following statements:
• The ATU internal bus master interface requests the internal bus when a PCI address
appears in an INPHQ and transaction ordering has been satisfied. The ATU takes
advantage of the information provided by the Relaxed Ordering Attribute bit.
• Once the internal bus is granted, the internal bus master interface drives the
translated address onto the bus. When a Retry is signaled, the request is repeated.
When a master abort occurs, the transaction is considered complete and an
unsupported request Completion is loaded into OCPLHQ for return to the PCI
Express requester (request is flushed once the completion has been posted to the
OCPLHQ).
• Once the translated address is on the bus and the transaction has been claimed,
the internal bus target starts returning data using a split response. Read data is
continuously received by the OCPLDQ until one of the following is true:
— The full byte count requested by the ATU read request is received. The internal
bus completer’s initiator interface performs an initiator completion in this case.
— A partial byte count requested by the ATU read request is received. The
completer’s internal bus initiator interface performs an initiator completion in
this case. Also, the completer reacquires the internal bus to deliver the
remaining read data byte count to the ATU.