Intel CONTROLLERS 413808 - Manual (Page 101)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 101
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.3.3 Inbound Read Completions Uncorrectable Data Errors
As an initiator, ATU may encounter this error condition when operating in PCI-X mode.
When as the completer of a Split Read Request the ATU observes
PERR# assertion
during the split completion transaction , the ATU attempts to complete the transaction
normally and no further action are taken.
2.7.3.4 Inbound Configuration Write Completion Message Uncorrectable Data
Errors
As an initiator, ATU may encounter this error condition when operating in PCI-X mode.
When as the completer of a Configuration (Split) Write Request the ATU observes
PERR# assertion during the split completion transaction , the ATU attempts to complete
the transaction normally and no further action are taken.
2.7.3.5 Inbound Read Request Uncorrectable Data Errors
2.7.3.5.1 Immediate Data Transfer
As a target, the ATU may encounter this error when operating in the Conventional PCI
or PCI-X modes.
Inbound read uncorrectable data errors occur when read data delivered from the IRQ is
detected as having bad parity by the initiator of the transaction who is receiving the
data. The initiator may optionally report the error to the system by asserting PERR# .
As a target device in this scenario, no action is required and no error bits are set.
2.7.3.5.2 Split Response Termination
As a target, the ATU may encounter this error when operating in the PCI-X mode.
Inbound read uncorrectable data errors occur during the Split Response Termination.
The initiator may optionally report the error to the system by asserting PERR# . As a
target device in this scenario, no action is required and no error bits are set.
2.7.3.6 Inbound Write Request Uncorrectable Data Errors
As a target, ATU may encounter this error when operating in Conventional or PCI-X
modes.
Uncorrectable Data errors occurring during write operations received by the ATU may
assert PERR# on the PCI Bus. When an error occurs, the ATU continues accepting data
until the initiator of the write transaction completes or a queue fill condition is reached.
Specifically, the following actions with the given constraints are taken by the ATU:
• PERR# is asserted two clocks cycles (three clock cycles when operating in PCI-X
mode) following the data phase in which uncorrectable data error is detected on
the bus. This is only done when the Parity Error Response bit in ATUCMD is set.
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction.