Intel CONTROLLERS 413808 - Manual (Page 53)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 53
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2 ATU Address Translation
The ATU allows PCI masters on the PCI bus to initiate transactions to the 4138xx
internal bus and allows the Intel XScale
®
processor (ARM* architecture compliant) to
initiate transactions to the PCI bus.
The ATU implements an address windowing scheme to determine which addresses to
claim and translate to the destination bus.
• The address windowing mechanism for inbound translation is described in Section
2.2.1.1, “Inbound Address Translation” on page 56
• The address windowing mechanism for outbound translation is described in Section
2.2.2, “Outbound Transactions- Single Address Cycle (SAC) Internal Bus
Transactions” on page 67 and Section 2.2.3, “Outbound Write Transaction” on
page 72
The ATU has the ability to accept up to eight inbound PCI read transactions and four
inbound PCI write transactions simultaneously. Also, the ATU has the ability to accept
up to eight outbound internal bus read transactions and four outbound internal bus
write transactions simultaneously. Refer to Figure 4 and Section 2.6 for details of the
ATU queue architecture.
The ATU unit allows for recognition and generation of multiple PCI cycle types.
Table 3
shows the PCI and PCI-X commands supported for both inbound and outbound ATU
transactions. The type of operation seen by the ATU on inbound transactions is
determined by the PCI master who initiates the transaction. Claiming an inbound
transaction depends on the address range programmed within the inbound translation
window. The type of transaction used by the ATU on outbound transactions generated
by the core processor is determined by the internal bus address and the outbound
windowing scheme.
ATU supports the 64-bit addressing specified by the PCI Local Bus Specification,
Revision 2.3. This 64-bit addressing extension is supported for both inbound and
outbound data transactions. This is in addition to the 64-bit data extensions supported
by the 4138xx.
ATU does not support exclusive access using the PCI LOCK# signal. Also, the ATU does
not insure atomicity for outbound transactions.
Note: In conventional PCI Mode, the ATUX will pre-fetch data for read transactions on the
internal bus as defined in Section 2.6.1.2, “Inbound Read Queue Structure” on
page 84 . For internal bus targets that are not capable of supporting large byte-counts
as indicated in Table 10, “Inbound Read Prefetch Data Sizes” on page 84 , these internal
bus targets must be accessed using a non-prefetchable PCI window. This requirement
also includes access made to the north internal bus targets via the internal bus bridge.
The internal bus bridge supports 32-byte data queues, and any access made via the
internal bus bridge that is greater than 32 bytes will result in an internal bus target
abort.