Intel CONTROLLERS 413808 - Manual (Page 66)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
66 Order Number: 317805-001US
2.2.1.5 Discard Timers
The ATU implements discard timers for inbound delayed transactions. These timers
prevent deadlocks when the initiator of a retried delayed transaction fails to complete
the transaction within 2
10
or 2
15
PCI clock cycles on the initiating bus when operating in
the conventional PCI mode. The timer starts counting when the delayed request
becomes a delayed completion by completing on the internal bus and all passing rules
are satisfied. When the originating master on the PCI bus has not retried the
transaction before the timer expires, the completion transaction is discarded.
Discard timer values are controlled by the ATU Configuration Register’s Discard Timer
Value bit. The ATU queues covered by discard timers are the IRQ and the IDWQ. After
discarding a transaction, the ATU must set the Discard Timer Status bit in the ATU
Configuration Register. The ATU does not assert the SERR# signal after discarding a
transaction.