Intel CONTROLLERS 413808 - Manual (Page 59)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 59
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2.1.2 Inbound Write Transaction
An inbound write transaction is initiated by a PCI master and is targeted at either
4138xx local memory or a 4138xx memory-mapped register.
Data flow for an inbound write transaction on the PCI bus is summarized as:
• The ATU claims the PCI write transaction when the PCI address is within the
inbound translation window defined by the ATU Inbound Base Address Register
(and Inbound Upper Base Address Register during DACs) and Inbound Limit
Register.
• When the IWADQ has at least one address entry available and the IWQ has at least
one buffer available, the address is captured and the first data phase is accepted.
• The PCI interface continues to accept write data until one of the following is true:
— The initiator performs a disconnect.
— The transaction crosses a buffer boundary.
• When an uncorrectable address error is detected during the address phase of the
transaction, the uncorrectable address error mechanisms are used. Refer to
Section 2.7.1 for details of the uncorrectable address error response.
• When operating in the PCI-X mode when an uncorrectable attribute error is
detected, the uncorrectable attribute error mechanism described in Section 2.7.1 is
used.
• When an uncorrectable data error is detected while accepting data, the slave
interface sets the appropriate bits based on PCI specification. No other action is
taken. Refer to Section 2.7.3.6 for details of the inbound write uncorrectable data
error response.
Once the PCI interface places a PCI address in the IWADQ, when IWQ has received
data sufficient to cross a buffer boundary or the master disconnects on the PCI bus, the
ATUs internal bus interface becomes aware of the inbound write. When there are
additional write transactions ahead in the IWQ/IWADQ, the current transaction remains
posted until ordering and priority have been satisfied (Refer to Section 2.6.3 ) and the
transaction is attempted on the internal bus by the ATU internal master interface. The
ATU does not insert target wait states nor do data merging on the PCI interface, when
operating in the PCI mode.
In the PCI-X mode memory writes are always executed as immediate transactions,
while configuration write transactions are processed as split transactions. The ATU
generates a Split Completion Message, (with Message class = 0h - Write Completion
Class and Message index = 00h - Write Completion Message) once a configuration write
is successfully executed.
Also, when operating in the PCI-X mode a write sequence may contain multiple write
transactions. The ATU handles such transactions as independent transactions.