Intel CONTROLLERS 413808 - Manual (Page 190)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
190 Order Number: 317805-001US
2.14.52 ATU Scratch Pad Register - ATUSPR
This register can be used for application specific purposes and has no direct impact on
the hardware.
2.14.53 PCI-X Capability Identifier Register - PCI-X_Cap_ID
The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus
Specification, Revision 2.3. This register in the PCI Extended Capability header
identifies the type of Extended Capability contained in that header. In the case of the
4138xx, this is the PCI-X extended capability with an ID of 07H as defined by the PCI-X
Protocol Addendum to the PCI Local Bus Specification, Revision 2.0.
Table 79. Scratch Pad Register - ATUSPR
Bit Default Description
31:0 0000H Scratch Pad Data - Entire register is available for application specific purposes.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0CCH
Table 80. PCI-X_Capability Identifier Register - PCI-X_Cap_ID
Bit Default Description
07:00 07H
Cap_Id - This field with its’ 07H value identifies this item in the linked list of Extended Capability
Headers as being the PCI-X capability registers.
PCI
IOP
Attributes
Attributes
7 4 0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
D0H
Register Offset
+0D0H