Figure 4. atu queue architecture block diagram, 4 atu queue architecture block diagram, Intel – Intel CONTROLLERS 413808 User Manual
Page 52
Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
52
Order Number: 317805-001US
Figure 4.
ATU Queue Architecture Block Diagram
PC
IB
us
In
te
rn
al
B
us
In
te
rf
ac
e
PC
IB
us
In
te
rfa
ce
ADDRESS TRANSLATION UNIT
In
te
rn
al
B
us
OWQ 4 KBytes
OWADQ
OTQ
IWQ 4 KBytes
IRQ 4 KBytes
IDWQ
(1 entry)
ITQ (8entries)
(8 entries)
(4 entries)
IWADQ
(4 entries)
ORQ 2 or 4 KBytes
B6321-01
See also other documents in the category Intel Computer Accessories:
- RAID AXXRSBBU6 (14 pages)
- IA-32 (636 pages)
- Evaluation Platform Board Manual RN (88 pages)
- ZT8101 (124 pages)
- CELERON 200 (53 pages)
- 210T (24 pages)
- AXXSW1GB (220 pages)
- I/O Controller Hub 6300ESB (14 pages)
- ARCHITECTURE IA-32 (568 pages)
- D15343-003 (166 pages)
- 1520 (176 pages)
- SR1450 (87 pages)
- 410 (60 pages)
- 460T (150 pages)
- SBC-455 (97 pages)
- cPCI-7200 (71 pages)
- 82600 (40 pages)
- 4.0A (10 pages)
- IXM5414E (294 pages)
- 520T (31 pages)
- NuPRO-850 (50 pages)
- Ethernet Switch Boards (52 pages)
- Express Hub (4 pages)
- SGI Altix 450 (198 pages)
- OPEN (660) 120/140/150 II (160 pages)
- 130T (18 pages)
- Express 100BASE-T4 (43 pages)
- PCI-7200 (65 pages)
- NetStructure 470 (155 pages)
- EXPRESS 330T (16 pages)
- TOUCH-N-MOW 120000 (12 pages)
- ETX CD (91 pages)
- SRW224P (2 pages)
- 410T (40 pages)