Intel CONTROLLERS 413808 - Manual (Page 712)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
712 Order Number: 317805-001US
14.6 Glitch Suppression Logic
The I
2
C Bus Interface Unit has built-in glitch suppression logic. Glitches are suppressed
according to: 2 * I
2
C clock period. For example, with the 33 MHz (30. ns period) I
2
C
clock glitches of 60ns or less are suppressed. This is within the 50 ns glitch suppression
specified.