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Intel CONTROLLERS 413808 User Manual

Page 15

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Intel

®

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

15

Contents—Intel

®

413808 and 413812

10.1 Overview ....................................................................................................... 565

10.2 Theory of Operation......................................................................................... 566

10.2.1 Interrupt Controller Unit........................................................................ 566

10.3 The Intel XScale

®

Processor Exceptions Architecture............................................ 567

10.3.1 CPSR and SPSR.................................................................................... 567

10.3.2 The Exception Process .......................................................................... 567

10.3.3 Exception Priorities and Vectors.............................................................. 568

10.3.4 Software Requirements For Exception Handling ........................................ 568

10.3.4.1 Nesting FIQ and IRQ Exceptions................................................ 568

10.4 Intel

®

413808 and 413812 I/O Controllers in TPER Mode External Interrupt Interface ....

569

10.4.1 Interrupt Inputs................................................................................... 569

10.4.2 Outbound Interrupts............................................................................. 571

10.5 The Intel

®

413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Unit...

572

10.5.1 Programmer Model ............................................................................... 573

10.5.1.1 Active Interrupt Source Control and Status................................. 573

10.5.1.2 Prioritization and Vector Generation for Active Interrupt Sources... 573

10.5.2 Operational Blocks................................................................................ 575

10.5.3 Intel

®

413808 and 413812 I/O Controllers in TPER Mode: Internal Peripheral

Interrupt576

10.5.3.1 Normal Interrupt Sources......................................................... 577

10.5.3.2 Error Interrupt Sources............................................................ 578

10.5.4 High-Priority Interrupt (

HPI#

)............................................................... 579

10.5.5 Timer Interrupts .................................................................................. 579

10.5.6 Inter-Processor Interrupts ..................................................................... 579

10.5.7 Intel XScale

®

Processor Interrupts ......................................................... 579

10.5.8 Software Interrupts .............................................................................. 579

10.6 Default Status................................................................................................. 580

10.7 Interrupt Control Unit Registers......................................................................... 581

10.7.1 Interrupt Base Register — INTBASE........................................................ 583

10.7.2 Interrupt Size Register — INTSIZE.......................................................... 584

10.7.3 IRQ Interrupt Vector Register — IINTVEC ................................................ 585

10.7.4 FIQ Interrupt Vector Register — FINTVEC ................................................ 586

10.7.5 Interrupt Pending Register 0 — INTPND0................................................. 587

10.7.6 Interrupt Pending Register 1 — INTPND1................................................. 588

10.7.7 Interrupt Pending Register 2 — INTPND2................................................. 589

10.7.8 Interrupt Pending Register 3 — INTPND3................................................. 590

10.7.9 Interrupt Control Register 0 — INTCTL0 .................................................. 591

10.7.10Interrupt Control Register 1 — INTCTL1 .................................................. 593

10.7.11Interrupt Control Register 2 — INTCTL2 .................................................. 595

10.7.12Interrupt Control Register 3 — INTCTL3 .................................................. 596

10.7.13Interrupt Steering Register 0 — INTSTR0 ................................................ 598

10.7.14Interrupt Steering Register 1 — INTSTR1 ................................................ 600

10.7.15Interrupt Steering Register 2 — INTSTR2 ................................................ 602

10.7.16Interrupt Steering Register 3 — INTSTR3 ................................................ 603

10.7.17IRQ Interrupt Source Register 0 — IINTSRC0........................................... 605

10.7.18IRQ Interrupt Source Register 1 — IINTSRC1........................................... 607

10.7.19IRQ Interrupt Source Register 2 — IINTSRC2........................................... 609

10.7.20IRQ Interrupt Source Register 3 — IINTSRC3........................................... 610

10.7.21FIQ Interrupt Source Register 0 — FINTSRC0........................................... 612

10.7.22FIQ Interrupt Source Register 1 — FINTSRC1........................................... 614

10.7.23FIQ Interrupt Source Register 2 — FINTSRC2........................................... 616

10.7.24FIQ Interrupt Source Register 3 — FINTSRC3........................................... 617

10.7.25Interrupt Priority Register 0 — IPR0........................................................ 619