Intel CONTROLLERS 413808 - Manual (Page 805)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 805
Peripheral Registers—Intel ® 413808 and 413812
19.6.1.6 GPIO
The GPIO block is allocated 64Bytes of PMMR registers space that is located at the
offset specified in Table 535 which is relative to the PMMRBAR.
Use the following equation to calculate the actual register address:
Internal Bus Address = PMMRBAR + GPIO Base Address Offset + Register Offset.
19.6.1.7 I
2
C Bus Interface Unit 0-2
The 4138xx contains three instances of the I
2
C Unit which are each allocated 32 Bytes
of PMMR registers space located at the offset specified in Table 537 .
Use the following equation to calculate the actual register address:
Internal Bus Address = PMMRBAR + I
2
C Base Address Offset + Register Offset.
Table 534. GPIO Offset.
Unit GPIO Base Address Offset Relative to PMMRBAR)
GPIO +2480H
Table 535. GPIO
Register Description (Name)
Register
Size in
Bits
Internal Bus Address Offset
(Relative to GPIO Base
Address Offset)
GPIO Output Enable Register — GPOE 32 +00H
GPIO Input Data Register — GPID 32 +04H
GPIO Output Data Register — GPOD 32 +08H
Reserved x +0CH–3FH
Table 536. I
2
C 0-2 Offset.
Unit I
2
C Base Address Offset (Relative to PMMRBAR)
I 2 C 0 +2500H
I 2 C 1 +2520H
I 2 C 2 +2540H
Table 537. I
2
C Unit
Register Description (Name)
Register
Size in
Bits
Internal Bus Address Offset
(Relative to I
2
C Base
Address Offset)
I 2 C Control Register x — ICRx 32 +00H
I 2 C Status Register x — ISRx 32 +04H
I 2 C Slave Address Register x — ISARx 32 +08H
I 2 C Data Buffer Register x — IBDRx 32 +0CH
Reserved 32 +10H
I 2 C Bus Monitor Register x — IBMRx 32 +14H
I 2 C Manual Bus Control Register x — IMBCRx 32 +18H
Reserved 32 +1CH