3 inbound doorbell register - idr, Table 268. inbound doorbell register - idr, 268 inbound doorbell register - idr – Intel CONTROLLERS 413808 User Manual

Page 413: Processor, Messaging unit—intel, Bit default description, Intel

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

413

Messaging Unit—Intel

413808 and 413812

4.7.3

Inbound Doorbell Register - IDR

The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale

processor. Bit 31 is reserved for generating an Error Doorbell interrupt. When bit 31 is

set, an Error interrupt may be generated to the Intel XScale

processor. All other bits,

when set, cause the Normal Messaging Unit interrupt line of the Intel XScale

processor to be asserted, when the interrupt is not masked by the Inbound Doorbell

Interrupt Mask bit in the Inbound Interrupt Mask Register. The bits in the IDR register

can only be set by an external Host I/O Interface agent and can only be cleared by the

Intel XScale

processor.

Table 268. Inbound Doorbell Register - IDR

Bit

Default

Description

Error Interrupt - Generate an Error Interrupt to the Intel XScale

processor.

30:00

00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale

processor.

When all bits are clear, do not generate a Normal Interrupt.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

MU/PCI Base Address Offset

IDR: 0020H

internal bus address offset

IDR: 4020H