Intel CONTROLLERS 413808 - Manual (Page 554)

Intel
®
413808 and 413812—Peripheral Bus Interface Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
554 Order Number: 317805-001US
9.3 Register Definitions
A series of configuration registers control PBI. Software can determine PBI status by
reading the status register. Table 363 lists all PBI registers which are detailed further in
proceeding sections.
Table 363. Peripheral Bus Interface Registers
Section, Register Name — Acronym (Page)
Section 9.3.1, “PBI Control Register — PBCR” on page 555
Section 9.3.2, “PBI Status Register — PBISR” on page 555
Section 9.3.4, “PBI Base Address Register 0 — PBBAR0” on page 557
Section 9.3.5, “PBI Limit Register 0 — PBLR0” on page 558
Section 9.3.6, “PBI Base Address Register 1 — PBBAR1” on page 559
Section 9.3.7, “PBI Limit Register 1 — PBLR1” on page 560
Section 9.3.8, “PBI Drive Strength Control Register — PBDSCR” on page 561
Section 9.3.9, “Processor Frequency Register - PFR” on page 562
Reserved.
Reserved.
Section 9.3.10, “External Strap Status Register 0 — ESSTSR0” on page 563
Reserved.
Section 9.3.12, “Unique ID Register 1 — UID1” on page 564