Intel CONTROLLERS 413808 - Manual (Page 453)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 453
SRAM DMA Unit (SDMA)—Intel
®
413808 and 413812
5.4.9 HostToLocal Source Upper Address Register - H2L_SUAR
The HostToLocal Source Upper Address Register (H2L_SUAR) represents the upper
32-bits of the source (host) address.
5.4.10 HostToLocal Source Lower Address Register - H2L_SLAR
The HostToLocal Source Lower Address Register (H2L_SLAR) represent the lower
32-bits of the source (host) address.
Table 307. HostToLocal Source Upper Address Register - H2L_SUAR
Bit Default Description
31:00 00000000H
Source Upper Address Register (SUAR) - Read/Write
This field specifies the upper-order 32 bits of the source (host) memory address. This field is CLEARED
by a hardware or software reset.
Coprocessor
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Intel XScale ® Microarchitecture internal bus address
offset
18258H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Table 308. HostToLocal Source Lower Address Register - H2L_SLAR
Bit Default Description
31:00 00000000H
Source Lower Address Register (SLAR) - Read/Write
This field specifies the low-order 32 bits of the source (host) memory address. This field is CLEARED by
a hardware or software reset.
Coprocessor
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Intel XScale ® Microarchitecture internal bus address offset
18254H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible