Intel CONTROLLERS 413808 - Manual (Page 75)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 75
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2.5 Outbound Configuration Cycle Translation
Outbound ATU provides a port programming model for outbound configuration cycles.
Performing an outbound configuration cycle to the PCI bus involves up to two internal
bus cycles:
1. Writing Outbound Configuration Cycle Address Register (OCCAR) with PCI address
used during configuration cycle. See the PCI-X Protocol Addendum to the PCI Local
Bus Specification, Revision 2.0 for information regarding configuration address
cycle formats. This IB bus cycle enables the transaction.
2. Writing or reading Outbound Configuration Cycle Data Register (OCCDR). A read
causes a configuration cycle read to the PCI bus with the address in the outbound
configuration cycle address register. Note that the Internal Bus read is executed as
a split transaction. Similarly, a write initiates a configuration cycle write to PCI with
the write data from the second processor cycle. Configuration cycles are non-burst
and restricted to a single 32-bit word cycle.
6
When the Configuration Cycle Data Register is written, data is latched and forwarded to
the PCI bus with the internal target issuing a single data phase disconnect with 32-bit
data only. This cycle does not receive an ACK64# from the ATU and therefore is
defined as 32-bit only.
Note, the programming model uses the register interface for outbound configuration
cycles, from a hardware standpoint, the address is entered into OTQ (reads) or OWADQ
(writes), configuration write data goes through OWQ and configuration read data is
returned in the ORQ.
Note: Outbound configuration cycle data registers are not physical registers. They are 4138xx
memory mapped addresses used to initiate a transaction with the address in the
associated address register.
2.2.5.1 PCI-X Mode 1 Considerations for Outbound Configuration Cycles
Configuration cycle address Bits 15:11 for Type 0 configuration cycles are defined
differently for Conventional versus PCI-X modes. When 4138xx software programs
OCCAR to initiate a Type 0 configuration cycle, always load OCCAR based on the PCI-X
definition for Type 0 configuration cycle address. In Conventional mode, 4138xx clears
OCCAR bits 15:11 prior to initiating an outbound Type 0 configuration cycle.
During the attribute phase of a Type 0 configuration transaction, the Secondary Bus
Number field (bits 7:0) is set equal to the Requester Bus Number (bits 15:8 of the
“PCI-X Status Register - PCIXSR” on page 193 ).
6. The designate the memory region containing OCCDR as non-cacheable and non-bufferable from
the Intel XScale
®
processor. This insures that all load/stores to OCCDR are only of DWORD
quantities. In event the user inadvertently issues a read to OCCDR that crosses a DWORD address
boundary, the ATU target aborts the transaction. All writes are terminated with a
Single-Phase-Disconnect and only bytes 3:0 is relevant.