Intel CONTROLLERS 413808 - Manual (Page 772)

Intel ® 413808 and 413812—Clocking and Reset
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
772 Order Number: 317805-001US
17.2.4 PCI Reset
This is the primary reset input for both the PCI Express and PCI/X interfaces. The
P_RST# reset clears all internal state machines and logic, and initialize all registers,
including sticky bits, to their default states. The assertion and deassertion of the PCI
reset signal P_RST# is asynchronous with respect to P_CLKIN / REFCLK+/- . The
rising edge of the P_RST# signal must be monotonic through the input switching
range and must meet the minimum slew rate. The PCI local bus specification defines
the assertion of P_RST# for a period of 1 ms after power is stable.
Upon the assertion of P_RST# , all units within the component are reset.
Upon the deassertion of P_RST# , the strapping pins are sampled to set configuration
modes (refer to Section 17.5, “Reset Strapping Options” on page 779 ).
17.2.5 PCI Express Hot Reset
The PCI Express* specification defines an in-band reset sequence that is used to reset
the link and downstream components. The Root Complex communicates the fact that it
is entering and coming out of a reset using these messages and the downstream
devices respond by also going through a reset. This incoming message by nature of the
PCI Express protocol is asynchronous to the reference clock.
As and End Point, the PCI Express Hot Reset clears all internal state machines and
logic, and initialize all registers to their default states except ‘sticky’ error bits which
are persistent through this reset.
As a root complex, the 4138xx can generate the reset message. In this case, the Hot
Reset does not cause a full chip reset and does not affect the internal logic.
17.2.6 WARM_RST# Reset Mechanism
The WARM_RST# reset clear all internal state machines and logic, and initialize all
registers to their default states except ‘sticky’ error bits which are persistent through
reset. To eliminate potential system reliability problems, all devices are also required to
either tristate their outputs or to drive them to safe levels during such a power on
reset.