Intel CONTROLLERS 413808 - Manual (Page 30)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
30 Order Number: 317805-001US
327 SGPIO Vendor Specific Code Register x - SGVSCRx .....................................................483
328 SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x.........................................484
329 Intel
®
413808 and 413812 I/O Controllers in TPER Mode Initiator IDs ...........................487
330 Address and Data Parity Testing Initiator IDs .............................................................489
331 Data Parity Testing Completer IDs ............................................................................489
332 Bridge supported Internal Bus Commands ................................................................491
333 Ordering and Passing Rules for both Inbound and Outbound Transactions ......................493
334 Internal Bus Arbitration Control Register — IBACR ......................................................499
335 South Internal Bus Address Test Control Register — SIBATCR ......................................501
336 South Internal Bus Data Test Control Register — SIBDTCR...........................................502
337 Peripheral Memory-Mapped Register Base Address Register — PMMRBAR.......................503
338 Memory Block Size Limit Register Value.....................................................................504
339 Bridge Window Base Address Register — BWBAR ........................................................505
340 Bridge Window Upper Base Address Register — BWUBAR.............................................506
341 Bridge Limit Register — BWLR..................................................................................507
342 Bridge Error Control and Status Register — BECSR......................................................508
343 Bridge Error Address Register — BERAR ....................................................................510
344 Bridge Error Upper Address Register — BERUAR .........................................................510
345 Commonly Used Terms ...........................................................................................512
346 Syndrome Decoding................................................................................................522
347 Data Parity Checking/Generation ..............................................................................529
348 SMCU Error Response .............................................................................................531
349 Memory Controller Register......................................................................................535
350 SRAM Base Address Register — SRAMBAR .................................................................536
351 SRAM Upper Base Address Register — SRAMUBAR ......................................................536
352 SRAM ECC Control Register — SECR..........................................................................537
353 SRAM ECC Log Register — SELOG.............................................................................538
354 SRAM ECC Address Register — SEAR.........................................................................540
355 SRAM ECC Context Address Register — SECAR...........................................................540
356 SRAM ECC Test Register — SECTST ..........................................................................541
357 SRAM Parity Control and Status Register — SPARCSR..................................................542
358 SRAM Parity Address Registers — SPAR.....................................................................543
359 SRAM Parity Upper Address Register — SPUAR ...........................................................543
360 SRAM Memory Controller Interrupt Status Register — SMCISR......................................544
361 Bus Signal Descriptions ...........................................................................................549
362 Flash Wait State Profile Programming
1
......................................................................552
363 Peripheral Bus Interface Registers ............................................................................554
364 PBI Control Register — PBCR ...................................................................................555
365 PBI Status Register — PBISR ...................................................................................555
366 Memory Block Size Limit Register Values ...................................................................556
367 PBI Base Address Register 0 — PBBAR0.....................................................................557
368 PBI Limit Register 0 — PBLR0...................................................................................558
369 PBI Base Address Register 1 — PBBAR1.....................................................................559
370 PBI Limit Register 1 — PBLR1...................................................................................560
371 PBI Drive Strength Control Register — PBDSCR ..........................................................561
372 Processor Frequency Register - PFR ..........................................................................562
373 External Strap Status Register 0 — ESSTS0 ...............................................................563
374 Unique ID Register 0 — UID0...................................................................................564
375 Unique ID Register 1 — UID1...................................................................................564
376 Exception Priorities And Vectors ...............................................................................568
377 Interrupt Input Pin Descriptions................................................................................570
378 Interrupt Output Pin Descriptions .............................................................................571
379 Normal Interrupt Sources ........................................................................................577
380 Error Interrupt Sources ...........................................................................................578
381 Default Interrupt Routing and Status Values...............................................................580