Intel CONTROLLERS 413808 - Manual (Page 116)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
116 Order Number: 317805-001US
2.7.9.1.2 Inbound Read Request
When operating in the Conventional mode, the following actions with the given
constraints are performed by the ATU when a master abort is detected by the internal
initiator interface during an inbound read transaction:
• Set the Internal Bus Master Abort bit (bit 7) in the ATUISR
• Return a target abort condition to the initiating master during the delayed
completion cycle on the PCI bus. No data is ever read from the internal bus and
returned to the PCI bus.
The following additional actions with the given constraints are performed by the ATU
when a target abort is signaled by the PCI interface during an inbound delayed read
completion cycle:
• Set the Target Abort (target) bit (bit 11) in the ATUSR.
• When the ATU PCI Target Abort (target) Interrupt Mask bit in the ATUIMR is clear,
set the PCI Target Abort (target) bit in the ATUISR. When set, no action.
• Flush the transaction that was master aborted from the ITQ after the target abort is
delivered on the PCI interface.
When operating in the PCI-X mode, the following actions with the given constraints are
performed by the ATU when a master abort is detected by the internal master interface
during an inbound split read transaction:
• Set the Internal Bus Master Abort bit (bit 7) in the ATUISR.
• Generate a Split Completion Error Message (with message class=2h - completer
error and message index=80h - 4138xx internal bus master abort) on the PCI bus.
• When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set,
no action.
• Flush the transaction that was master aborted.
Note: This split completion error message includes a device specific message index. The error
handler would need to have knowledge of the device specific error messages of the
4138xx in order to fully diagnose the problem.
The Internal Bus Master Abort bit is non-maskable and always results in an interrupt
being driven to the core processor.