5 sram ecc address register - sear, Table 354. sram ecc address register - sear, 6 sram ecc context address register - secar – Intel CONTROLLERS 413808 User Manual

Page 540: 5 sram ecc address register — sear, 6 sram ecc context address register — secar, 354 sram ecc address register — sear, 355 sram ecc context address register — secar, Table 354. sram ecc address register — sear, Intel, Bit default description

Intel

413808 and 413812—SRAM Memory Controller

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

540

Order Number: 317805-001US

8.6.5

SRAM ECC Address Register — SEAR

This register is responsible for logging the address where the error was detected on the

local memory bus. One error can be detected and logged. The software knows which

SRAM address had the error by reading this register and decoding the syndrome in the

log register. The upper 4 bits are captured in the SECR — refer to

Section 8.6.3, SRAM

ECC Control Register — SECR

. For error details, see

Section 8.3.3, “Error Correction

and Detection” on page 519

8.6.6

SRAM ECC Context Address Register — SECAR

This register is responsible for logging the descriptor tag of the descriptor while the

ECC error was detected on the local memory bus. One error can be detected and

logged. The software knows which descriptor was being processed by reading this

Table 354. SRAM ECC Address Register — SEAR

Bit

Default

Description

31:02

Error Address: Stores the lower 30 bits of the address that resulted in a single bit or multi-bit error.

01:00

Reserved

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale

processor Local Bus Address Offset

+1510H

Table 355. SRAM ECC Context Address Register — SECAR

Bit