Uarts—intel, Bit default description – Intel CONTROLLERS 413808 User Manual

Page 681

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

681

UARTs—Intel

413808 and 413812

Transmit Data Request (TDRQ): Indicates that the UART is ready to accept data for
transmission. The assertion of this bit causes the UART to issue an interrupt when
the Transmit Data Request Interrupt Enable is set.

In non-FIFO mode, the TDRQ bit is set (1) when a character is transferred from the
Transmit-Holding register. The bit is cleared (0) concurrently with the loading of the
Transmit Holding register by the processor.

In FIFO mode, TDRQ is set (1) when the FIFO is less than half full. It is cleared when
the FIFO is more than half full. When more than 64 characters are loaded into the
FIFO, the excess characters are lost.

0 = The UART is NOT ready to receive data for transmission.
1 = The UART is ready to receive data for transmission.

Break Indicator (BI): Set (1) when the received data input is held in the Spacing
(logic 0) state for longer than a full character transmission time (that is, the total time
of start bit + data bits + parity bit + stop bits). The Break Indicator is reset (cleared to
0) when the processor reads the Line-Status register.

In FIFO mode, only one Break character (equal to 0x00), is loaded into the FIFO
regardless of the length of the Break condition. BI shows the Break condition for the
character at the bottom of the FIFO, not the most recent character received.

0 = No break signal has been received.
1 = Break signal has been received.

Framing Error (FE): Indicates that the received character did not have a valid stop
bit. FE is set (1) when the bit following the last data bit or parity bit is detected as a
logic 0 bit (spacing level). When the Line Control register had been set for two stop
bits, the receiver does not check for a valid second stop bit. The FE indicator is reset
when the processor reads the Line Status Register.

The UART resynchronizes after a framing error by assuming that the framing error
was due to the next start bit. Therefore it samples this start bit twice and then takes in
the data.

In FIFO mode, FE shows a framing error for the character at the bottom of

the FIFO, not for the most recently received character.

0 = No Framing error.
1 = Invalid stop bit has been detected.

Table 455. UART x Line Status Register - (UxLSR) (Sheet 2 of 3)

Bit

Default

Description

Unit #

Intel XScale

Core internal bus address

+2314H (DLAB=x)

+2354H (DLAB=x)

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible