Intel CONTROLLERS 413808 - Manual (Page 702)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
702 Order Number: 317805-001US
14.3.4 Master Operations
When software initiates a read or write on the I
2
C bus, the I
2
C unit transitions from the
default slave-receive mode to master-transmit mode. The start pulse is sent followed
by the 7-bit slave address and the R/W# bit. After the master receives an
acknowledge, the I
2
C unit has the option of two master modes:
• Master-Transmit — The 4138xx writes data
• Master-Receive — The 4138xx reads data
The 4138xx initiates a master transaction by writing to the ICR register. Data is read
and written from the I
2
C unit through the memory-mapped registers.
Table 467 describes the I
2
C Bus Interface Unit responsibilities as a master device.
Table 467. Master Transactions (Sheet 1 of 2)
I
2
C Master
Action
Mode of
Operation
Definition
Generate clock
output
Master-transmit
Master-receive
• The master always drives the SCL line.
• The SCL Enable bit must be set.
• The Unit Enable bit must be set.
Write target
slave address to
IDBR
Master-transmit
Master-receive
• The Intel XScale ® processor writes to IDBR bits 7-1 before a START condition is
enabled.
• First 7 bits sent on bus after START.
• See Section 14.2.3 .
Write R/W# Bit
to IDBR
Master-transmit
Master-receive
• The Intel XScale ® processor writes to the least significant IDBR bit with the target slave
address.
• When low, the master remains a master-transmitter. When high, the master transitions
to a master-receiver.
• See Section 14.3.1 .
Signal START
Condition
Master-transmit
Master-receive
• See “Generate clock output” above.
• Performed after the target slave address and the R/W# bit are in the IDBR.
• Intel XScale ® processor sets the START bit.
• Intel XScale ® processor sets the Transfer Byte bit which initiates the start condition.
• See Section 14.2.3 .
Initiate first data
byte transfer
Master-transmit
Master-receive
• Intel XScale ® processor writes byte to IDBR
• I 2 C Bus Interface Unit transmits the byte when the Transfer Byte bit is set.
• I 2 C Bus Interface Unit clears the Transfer Byte bit and sets the IDBR Transmit Empty bit
when the transfer is complete.
Arbitrate for I 2 C
Bus
Master-transmit
Master-receive
• When two or more masters signal a start within the same clock period, arbitration must
occur.
• The I 2 C Bus Interface Unit arbitrates for as long as necessary. Arbitration takes place
during slave address, R/W# bit, and data transmission and continues until all but one
master loses the bus. No data is lost during arbitration.
• When the I 2 C Bus Interface Unit loses arbitration, it sets the Arbitration Loss Detect ISR
bit after byte transfer is complete and transition to slave-receive (default) mode.
• When I 2 C Bus Interface Unit loses arbitration while attempting to send the target
address byte, the I 2 C Bus Interface Unit attempts to resend it when the bus becomes
free.
• The system designer must ensure the boundary conditions described in Section 14.3 do
not occur.
Write one data
byte to the IDBR
Master-transmit
only
• Data transmit mode of I 2 C master operation.
• Occurs when the IDBR Transmit Empty ISR bit is set and the Transfer Byte bit is clear.
When enabled, the IDBR Transmit Empty Interrupt is signalled to the Intel XScale ®
processor.
• Intel XScale ® processor writes 1 data byte to the IDBR, set the appropriate
START/STOP bit combination, and then set the Transfer Byte bit to send the data. Eight
bits are written on the serial bus followed by a STOP when requested.