Intel CONTROLLERS 413808 - Manual (Page 115)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 115
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.9 Internal Bus Error Conditions
An internal bus error results in a bit being set in the Interrupt Status Registers at which
time an interrupt is driven to the Intel XScale
®
processor. Unlike PCI errors, internal
bus error conditions are not maskable.
The following sections detail internal bus error conditions for the ATU.
2.7.9.1 Master Abort on the Internal Bus
A master abort on the internal bus is seen by the ATU when the inbound translated
address presented on the internal bus is not claimed.
2.7.9.1.1 Inbound Write Request
The following action with the given constraints are performed by the ATU when a
master abort is detected by the internal master interface during an inbound write
request transaction:
• Set the Internal Bus Master Abort bit (bit 7) in the ATUISR.
• When the Inbound Error SERR# Enable bit is set in the ATUIMR and the SERR#
Enable bit is set in the ATUCMD, assert SERR# on the PCI interface. When both
bits are not set, take no action. When SERR# is asserted, additional actions are
taken:
— Set the SERR# Asserted bit in the ATUSR
— When the ATU SERR# Asserted Interrupt Mask bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action
— When the ATU SERR# Detected interrupt enable is set in the ATUCR, set the
SERR# Detected bit in the ATUISR. When clear, no action
• Flush the transaction that was master aborted from the IWQ.
The Internal Bus Master Abort bit is non-maskable and always results in an interrupt
being driven to the core processor.