Intel CONTROLLERS 413808 - Manual (Page 347)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 347
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.61 PCI Express Link Capabilities Register - PE_LCAP
This register identifies the capabilities and current operating mode of ATU, DMAs and
Message Unit when operating in the PCI Express mode.
Table 201. PCI Express Link Capabilities Register - PE_LCAP
Bit Default Description
31:24 00H Port # - PCI Express port number.
23:18 00H Preserved
17:15 111b L1 Exit Latency- Active State L1 Transition not supported
14:12 001b L0s Exit Latency - 64ns - 128ns.
11:10 01b Active State Link PM Support
9:4 08H Maximum Link Width - This device supports a maximum width of x8.
3:0 1H Maximum Link Speed - The PCI Express Link operates at 2.5 Gb/s.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0DCH