42 atu interrupt status register - atuisr, 42atu interrupt status register - atuisr, 182 atu interrupt status register - atuisr – Intel CONTROLLERS 413808 User Manual

Page 329: Atu interrupt status register, Address translation unit (pci express)—intel, Bit default description

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

329

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.42 ATU Interrupt Status Register - ATUISR

The ATU Interrupt Status Register is used to notify the core processor of the source of

an ATU interrupt. In addition, this register is written to clear the source of the interrupt

to the interrupt unit of the 4138xx. All bits in this register are Read/Clear.
Bits 4:0 are a direct reflection of bits 15, 13:11, and bit 8 (respectively) of the ATU

Status Register (these bits are set at the same time by hardware but need to be

cleared independently). Bit 5 is set by an error associated with the internal bus of the

4138xx. Bit 24 is for software BIST. The conditions that result in an ATU interrupt are

cleared by writing a 1 to the appropriate bits in this register.

Note:

The interrupt status bits are not set when the corresponding mask bit is set.

Table 182. ATU Interrupt Status Register - ATUISR (Sheet 1 of 3)

Bit

Default

Description

31:29

Reserved Zero - Software must write 0 to these bits.

Slot Power Message Received - Indicates a Set_Slot_Power_Limit Message was received and logged in

the

“PCI Express Device Capabilities Register - PCIE_DCAP” on page 343

Generates the ATU Inbound Message Interrupt.

PME Interrupt - Indicates a PME message was received and logged in the

“PCI Express Root Status

Note:

This read only bit is a copy of the start PME Status bit in the PE_RSR register. To clear this

interrupt software must clear the PME Status bit. The “mask” for this interrupt is controlled by

the PME interrupt enable in the

“PCI Express Root Control Register - PE_RCR” on page 353

Generates the ATU Inbound Message Interrupt

Hot-Plug Message Received - This bit set when a Hot-Plug message is received that changes the value of

the Attention Indicator Status or Power Indicator Status in the

“PCI Express Message Control and Status

Generates the ATU Inbound Message Interrupt

Inbound Vendor Message Received (IVM) - Note while this bit is asserted, any additional Inbound

Vendor Messages may be blocked which can block all other inbound transactions. This bit must be

cleared after the message has been processed. See

Section 3.3.1.6, “Inbound Vendor_Defined Message

Transactions” on page 243

for more details.

Generates the ATU Inbound Message Interrupt

ATU BIST Interrupt - When set, the host processor has set the start BIST, ATUBISTR register bit 6, and

the ATU BIST interrupt enable (ATUCR register bit 3) is enabled. The Intel XScale

processor can initiate

the software BIST and store the result in ATUBISTR register bits 3:0.

Note:

This read only bit is a copy of the start BIST bit in the ATUBISTR register. To clear this interrupt

software must clear the start BIST bit. The “mask” for this interrupt is controlled by the BIST

interrupt enable in the ATUCR register.

Generates the ATU BIST Interrupt

23:19

Reserved Zero - Software must write 0 to these bits.

ATU Configuration Write - This bit is set when a PCI Express configuration write occurs to any enabled

function. When set, this bit results in the assertion of the ATU Config Reg Write Interrupt.

PCI

IOP

Attributes

Attribute Legend:

RZ = Reserved Zero

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+078H