Intel CONTROLLERS 413808 User Manual
Page 817
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
817
Peripheral Registers—Intel
®
413808 and 413812
PCI Express Uncorrectable Error Severity — ERRUNC_SEV
32
+10CH
PCI Express Correctable Error Status — ERRCOR_STS
32
+110H
PCI Express Correctable Error Mask — ERRCOR_MSK
32
+114H
Advanced Error Control and Capability Register — ADVERR_CTL
32
+118H
PCI Express Advanced Error Header Log — ADVERR_LOG0
32
+11CH
PCI Express Advanced Error Header Log — ADVERR_LOG1
32
+120H
PCI Express Advanced Error Header Log — ADVERR_LOG2
32
+124H
PCI Express Advanced Error Header Log — ADVERR_LOG3
32
+128H
Root Error Command Register — RERR_CMD
32
+12CH
Root Error Status Register — RERR_SR
32
+130H
Error Source Identification Register RERR_ID
32
+134H
Reserved.
32
+140H
Reserved.
32
+144H
Reserved.
32
+148H
Reserved.
32
+14CH
Reserved.
x
+150H through +1DFH
Device Serial Number Capability — DSN_CAP
32
+1E0H
Device Serial Number Lower DW Register — DSN_LDW
32
+1E4H
Device Serial Number Upper DW Register — DSN_UDW
32
+1E8H
Power Budgeting Enhanced Capability Header — PWRBGT_CAPID
32
+1F0H
Power Budgeting Data Select Register — PWRBGT_DSEL
32
+1F4H
Power Budgeting Data Register — PWRBGT_DATA
32
+1F8H
Power Budgeting Capability Register — PWRBGT_CAP
32
+1FCH
Power Budgeting Information Registers[0:23] — PWRBGT_INFO[0:23]
32 x24
+200H through +25CH
Reserved.
x
+260H through +2FFH
Outbound I/O Base Address Register — OIOBAR
32
+300H
Outbound I/O Window Translate Value Register — OIOWTVR
32
+304H
Outbound Upper Memory Window Base Address Register 0 — OUMBAR0
32
+308H
Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0
32
+30CH
Outbound Upper Memory Window Base Address Register 1 — OUMBAR1
32
+310H
Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1
32
+314H
Outbound Upper Memory Window Base Address Register 2- OUMBAR2
32
+318H
Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2
32
+31CH
Outbound Upper Memory Window Base Address Register 3 — OUMBAR3
32
+320H
Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3
32
+324H
Reserved.
32
+328H
Outbound Configuration Cycle Address Register — OCCAR
32
+32CH
Outbound Configuration Cycle Data Register — OCCDR
32
+330H
Outbound Configuration Cycle Function Number — OCCFN
32
+334H
Reserved.
x
+338H through +33FH
Inbound Vendor Defined Message Header Register0 — IVMHR0
32
+340H
Inbound Vendor Defined Message Header Register 1 — IVMHR1
32
+344H
Inbound Vendor Defined Message Header Register 2 — IVMHR2
32
+348H
Inbound Vendor Defined Message Header Register 3 — IVMHR3
32
+34CH
Table 546. Address Translation Unit Registers — ATUE (Sheet 3 of 4)
Register Description (Name)
Register
Size in
Bits
Internal Bus Address Offset
(Relative to ATUE Base
Address Offset)
Notes:
1.
MSI and MSI-X Capability Registers are documented in the Messaging Unit Chapter.