Intel CONTROLLERS 413808 - Manual (Page 435)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 435
Messaging Unit—Intel
®
413808 and 413812
4.7.26 MSI-X Capability Identifier Register - MSI-X_Cap_ID
The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus
Specification, Revision 2.3. This register in the PCI Extended Capability header
identifies the type of Extended Capability contained in that header. In the case of the
4138xx, this is the MSI-X extended capability with an ID of 0DH as defined by the
PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0.
Note: Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 291. MSI-X_Capability Identifier Register - MSI-X_Cap_ID
Bit Default Description
07:00 0DH
Cap_Id - This field with its’ 0DH value identifies this item in the linked list of Extended Capability
Headers as being the MSI-X capability registers.
PCI
IOP
Attributes
Attributes
7 4 0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
B0H
Internal Bus Address Offset
0B0H