Intel CONTROLLERS 413808 - Manual (Page 728)

Intel ® 413808 and 413812—General Purpose I/O Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
728 Order Number: 317805-001US
15.2.3 GPIO Output Data Register — GPOD
The GPIO Output Data Register is driven on a per bit basis on the appropriate GPIO
bus pins following the deassertion of P_RST# when the corresponding bit in the GPOE
register is cleared.
Table 480. GPIO Output Data Register — GPOD
Bit Default Description
31:16 0000H Reserved.
15 0
2
GPIO15 Output Data — This bit value is driven on the GPIO[15] pin when bit[15] of the GPOE register
is cleared.
14 0
2
GPIO14 Output Data — This bit value is driven on the GPIO[14] pin when bit[14] of the GPOE register
is cleared.
13 0
2
GPIO13 Output Data — This bit value is driven on the GPIO[13] pin when bit[13] of the GPOE register
is cleared.
12 0
2
GPIO12 Output Data — This bit value is driven on the GPIO[12] pin when bit[12] of the GPOE register
is cleared.
11 0
2
GPIO11 Output Data — This bit value is driven on the GPIO[11] pin when bit[11] of the GPOE register
is cleared.
10 0
2
GPIO10 Output Data — This bit value is driven on the GPIO[10] pin when bit[10] of the GPOE register
is cleared.
09 0
2
GPIO9 Output Data — This bit value is driven on the GPIO[9] pin when bit[9] of the GPOE register is
cleared.
08 0
2
GPIO8 Output Data — This bit value is driven on the GPIO[8] pin when bit[8] of the GPOE register is
cleared.
07 0
2
GPIO7 Output Data — This bit value is driven on the GPIO[7] pin when bit[7] of the GPOE register is
cleared.
06 0
2
GPIO6 Output Data — This bit value is driven on the GPIO[6] pin when bit[6] of the GPOE register is
cleared.
05 0
2
GPIO5 Output Data — This bit value is driven on the GPIO[5] pin when bit[5] of the GPOE register is
cleared.
04 0
2
GPIO4 Output Data — This bit value is driven on the GPIO[4] pin when bit[4] of the GPOE register is
cleared.
03 0
2
GPIO3 Output Data — This bit value is driven on the GPIO[3] pin when bit[3] of the GPOE register is
cleared.
02 0
2
GPIO2 Output Data — This bit value is driven on the GPIO[2] pin when bit[2] of the GPOE register is
cleared.
01 0
2
GPIO1 Output Data — This bit value is driven on the GPIO[1] pin when bit[1] of the GPOE register is
cleared.
00 0
2
GPIO0 Output Data — This bit value is driven on the GPIO[0] pin when bit[0] of the GPOE register is
cleared.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address offset
+2488H