Intel CONTROLLERS 413808 - Manual (Page 359)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 359
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.74 PCI Express Correctable Error Mask - ERRCOR_MSK
The Correctable Error Mask register controls reporting of individual correctable errors
via ERR_COR message. A masked error (respective bit set in mask register) is not
reported to the PCI Express Root Complex. There is a mask bit per error bit in the
Correctable Error Status register.
Note: All bits in this register are sticky through reset.
Table 214. PCI Express Correctable Error Mask - ERRCOR_MSK
Bit Default Description
31:14 0 Preserved.
13 1
Advisory Non-Fatal Error Mask - this bit is set by default to enable compatibility with software that does
not comprehend Role-Based Error Reporting.
12 0 Replay Timer Timeout Mask
11:9 0 Preserved.
8 0 REPLAY_NUM Rollover Mask
7 0 Bad DLLP Mask
6 0 Bad TLP Mask
5:1 0 Preserved.
0 0 Receiver Error Mask
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
rw
rw
pr
pr
pr
pr
pr
pr
rw
rw
rw
rw
rw
rw
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
S S S S S S
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+114H