2 theory of operation – Intel CONTROLLERS 413808 User Manual
Page 399
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
399
Messaging Unit—Intel
®
413808 and 413812
4.2
Theory of Operation
The MU has two independent messaging mechanisms. The Message Registers are
similar to a combination of mailbox and doorbell registers. Each holds a 32-bit value
and generates an interrupt when written. The two Doorbell Registers support software
interrupts. When a bit is set in a Doorbell Register, an interrupt is generated.
Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register
and the Outbound Interrupt Status Register. Each interrupt generated by the Messaging
Unit can be masked.
Because of read side effects, multi-word burst transactions are not supported by the
Messaging Unit. The Messaging Unit must be mapped in a non-prefetchable PCI
address space to avoid read side effects. Multi-word read or write transactions made to
the Messaging Unit registers causes the MU to generate an address error on the
internal bus of the 4138xx. Multi-word transactions made by an external PCI agent
results in an error being sent to the external PCI agent. Refer to the ATU chapters for
more details on how the ATUs respond to an internal bus error.
All registers needed to configure and control the Messaging Unit are memory-mapped
registers.
The MU is accessed by an external PCI agent via the ATU. The MU can be mapped in
any 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
The MU provides the Base Address Registers (
Table 278, “MU Base Address Register -
“MU Upper Base Address Register - MUUBAR”
) which allow the MU to be
relocated within the ATU translated window. This PCI address window is used for PCI
transactions that access the 4138xx local memory. The PCI address of the inbound
translation window is contained in the Inbound ATU Base Address Register. See
Chapter 2.0, “Address Translation Unit (PCI-X)”
Chapter 3.0, “Address Translation
for more details on inbound ATU addressing and the ATU.
Note that since the MU is located on the internal bus of the 4138xx, any PCI transaction
that is targeted for the MU is first claimed by the ATU and then the ATU issues the
transaction on the internal bus of the 4138xx.