Intel CONTROLLERS 413808 - Manual (Page 165)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 165
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
Table 50. ATU Base Registers and Associated Limit Registers
Base Address Register Limit Register
a
Description
Inbound ATU Base Address
Register 0
Inbound ATU Limit Register 0
Defines the inbound translation
window 0 from the PCI bus.
Inbound ATU Upper Base Address
Register 0
N/A
Together with ATU Base Address
Register 0 defines the inbound
translation window 0 from the PCI
bus for DACs.
Inbound ATU Base Address
Register 1
Inbound ATU Limit Register 1
Defines the inbound translation
window 1 from the PCI bus.
Inbound ATU Upper Base Address
Register 1
N/A
Together with ATU Base Address
Register 1 defines the inbound
translation window 1 from the PCI
bus for DACs.
Inbound ATU Base Address
Register 2
Inbound ATU Limit Register 2
Defines the inbound translation
window 2 from the PCI bus.
Inbound ATU Upper Base Address
Register 2
N/A
Together with ATU Base Address
Register 2 defines the inbound
translation window 2 from the PCI
bus for DACs.
Inbound ATU Base Address
Register 3
Inbound ATU Limit Register 3
Defines the inbound translation
window 3 from the PCI bus.
Inbound ATU Upper Base Address
Register 3
N/A
Together with ATU Base Address
Register 3 defines the inbound
translation window 3 from the PCI
bus for DACs.
Note: This is a private BAR that
resides outside of the
standard PCI configuration
header space (offsets
00H-3FH).
Expansion ROM Base Address
Register
Expansion ROM Limit Register
Defines the window of addresses
used by a bus master for reading
from an Expansion ROM.
a. For Inbound Memory Windows 0-2, bit 0 of the limit register is a “claiming disable” bit. This feature allows the
Memory Window to be used to a Memory Range for use in communication with Private PCI devices.