Intel CONTROLLERS 413808 - Manual (Page 302)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
302 Order Number: 317805-001US
3.17.11 ATU Header Type Register - ATUHTR
Header Type Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3.
This register indicates the layout of ATU configuration space bytes 10H to 3FH. The
MSB indicates whether or not the device is multi-function.
Table 150. ATU Header Type Register - ATUHTR
Bit Default Description
07
End Point:
DF_SEL[2:0]
!=
“000”
Root
Complex:
0
Single Function/Multi-Function Device - Identifies the 4138xx as a single-function or multi-function PCI
device depending on the setting of the DF_SEL[2:0] strap during P_RST# assertion.
Note: The 4138xx can be configured as a single-function device (ATU only) or a multi-function device
(ATU and storage controller) for split driver support.
As a Root Complex this bit is always ‘0’.
06:00 000000
2
PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface header
conforms to PCI Local Bus Specification, Revision 2.3.
PCI
IOP
Attributes
Attributes
7 4 0
ro
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+00EH