Intel CONTROLLERS 413808 - Manual (Page 550)

Intel
®
413808 and 413812—Peripheral Bus Interface Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
550 Order Number: 317805-001US
9.2.6 Flash Memory Support
Note: Be sure to refer to the System Software Architecture Specification and Design Guide for
details on supported Flash parts, since the Transport Firmware must provide support
for the Flash device in addition to PBI.
PBI peripheral bus interface supports 8-, or 16- bit Flash devices.
The PBI provides programmable wait state functionality for peripheral memory
windows.
Note: Potentially, programmable wait state functionality could be connected to any peripheral
device that has a deterministic wait state profile. However, data valid and turn-around
times would need to fit within parameters provided by programmable wait state profiles
to support Flash devices.
Any write transactions issued to a Flash address space window must always represent a
single flash bus data cycle ( strb, strh ).
The peripheral chip enables, PCE[1:0]# , activate the appropriate Peripheral window
when the address falls within one of the Peripheral address ranges.
Note: By default, bank 0 is enabled with the maximum number of Address-to-Data and
Recovery Wait states. The width of the interface can be strapped for either 8-bit wide
Flash or 16-bit wide flash. Thus, PCE0# is the Peripheral Bus chip enable to be used for
booting purposes.
Figure 64 on page 550 illustrates how two 8-bit Flash devices would interface with an
Intel XScale
®
processor through the PBI Interface.
Figure 64. Sixty-Four Mbyte Flash Memory System
A[24:00]
POE#
PWE#
PCE0#
PCE1#
Intel® 81348
I/O Processor
A[24:0]
OE#
WE#
DQ[7:0]
CE#
Intel®
28F256J3
256 Mbit
Flash
A[24:00]
D[15:0]
PB_RSTOUT#
RST#
D[07:00]
A[24:0]
OE#
WE#
DQ[7:0]
CE#
Intel®
28F256J3
256 Mbit
Flash
RST#
B6267-01