Intel CONTROLLERS 413808 - Manual (Page 11)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 11
Contents—Intel
®
413808 and 413812
3.17.111Outbound Vendor Message Header Register 1 - OVMHR1.......................... 389
3.17.112Outbound Vendor Message Header Register 2 - OVMHR2.......................... 390
3.17.113Outbound Vendor Message Header Register 3 - OVMHR3.......................... 390
3.17.114Outbound Vendor Message Payload Register - OVMPR.............................. 391
3.17.115PCI Interface Error Control and Status Register - PIE_CSR ....................... 392
3.17.116PCI Interface Error Status - PIE_STS ..................................................... 393
3.17.117PCI Interface Error Mask - PIE_MSK ...................................................... 394
3.17.118PCI Interface Error Header Log - PIE_LOG0............................................ 395
3.17.119PCI Interface Error Header Log 1 - PIE_LOG1 ......................................... 395
3.17.120PCI Interface Error Header Log 2 - PIE_LOG2 ......................................... 396
3.17.121PCI Interface Error Header Log - PIE_LOG3............................................ 396
3.17.122PCI Interface Error Descriptor Log......................................................... 397
3.17.123ATU Reset Control Register - ATURCR.................................................... 397
4.0 Messaging Unit......................................................................................................... 398
4.1 Overview ....................................................................................................... 398
4.2 Theory of Operation......................................................................................... 399
4.2.1 Transaction Ordering ............................................................................ 402
4.3 Message Registers........................................................................................... 403
4.3.1 Outbound Messages.............................................................................. 403
4.3.2 Inbound Messages................................................................................ 403
4.4 Doorbell Registers ........................................................................................... 404
4.4.1 Outbound Doorbells.............................................................................. 404
4.4.2 Inbound Doorbells................................................................................ 404
4.5 Messaging Unit Error Conditions ........................................................................ 405
4.6 Message-Signaled Interrupts............................................................................. 406
4.6.1 MSI Capability Structure ....................................................................... 406
4.6.2 MSI-X Capability and Table Structures .................................................... 407
4.6.3 Level-Triggered Versus Edge-Triggered Interrupts .................................... 409
4.7 Register Definitions ......................................................................................... 410
4.7.1 Inbound Message Register - IMRx........................................................... 412
4.7.2 Outbound Message Register - OMRx ....................................................... 412
4.7.3 Inbound Doorbell Register - IDR............................................................. 413
4.7.4 Inbound Interrupt Status Register - IISR................................................. 414
4.7.5 Inbound Interrupt Mask Register - IIMR .................................................. 415
4.7.6 Outbound Doorbell Register - ODR.......................................................... 416
4.7.7 Outbound Interrupt Status Register - OISR.............................................. 417
4.7.8 Outbound Interrupt Mask Register - OIMR ............................................... 418
4.7.9 Inbound Reset Control and Status Register - IRCSR .................................. 419
4.7.10 Outbound Reset Control and Status Register - ORCSR............................... 420
4.7.11 MSI Inbound Message Register — MIMR .................................................. 421
4.7.12 MU Configuration Register - MUCR.......................................................... 422
4.7.13 MU Base Address Register - MUBAR........................................................ 423
4.7.14 MU Upper Base Address Register - MUUBAR............................................. 424
4.7.15 MU MSI-X Table Message Address Registers - M_MT_MAR[0:7] .................. 425
4.7.16 MU MSI-X Table Message Upper Address Registers - M_MT_MUAR[0:7] ....... 426
4.7.17 MU MSI-X Table Message Data Registers - M_MT_MDR[0:7]....................... 427
4.7.18 MU MSI-X Table Message Vector Control Registers - M_MT_MVCR[0:7]........ 428
4.7.19 MU MSI-X Pending Bits Array Register - M_MPBAR.................................... 429
4.7.20 MSI Capability Identifier Register - Cap_ID.............................................. 429
4.7.21 MSI Next Item Pointer Register - MSI_Next_Ptr........................................ 430
4.7.22 Message Control Register - Message_Control ........................................... 431
4.7.23 Message Address Register - Message_Address.......................................... 432
4.7.24 Message Upper Address Register - Message_Upper_Address ...................... 433
4.7.25 Message Data Register- Message_Data ................................................... 434