Intel CONTROLLERS 413808 - Manual (Page 4)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
4 Order Number: 317805-001US
2.2.6 Internal Bus Operation ............................................................................77
2.3 Big Endian Byte Swapping...................................................................................78
2.3.1 Inbound Byte Swapping...........................................................................78
2.3.2 Outbound Byte Swapping.........................................................................79
2.4 CompactPCI Hot-Swap .......................................................................................80
2.4.1 Pin Interface ..........................................................................................80
2.4.1.1 Compact PCI Hot-Swap Mode Select ............................................81
2.5 Expansion ROM Translation Unit...........................................................................82
2.6 ATU Queue Architecture......................................................................................83
2.6.1 Inbound Queues.....................................................................................83
2.6.1.1 Inbound Write Queue Structure...................................................83
2.6.1.2 Inbound Read Queue Structure ...................................................84
2.6.1.3 Inbound Delayed Write Queue.....................................................85
2.6.1.4 Inbound Transaction Queues Command Translation Summary.........85
2.6.2 Outbound Queues...................................................................................86
2.6.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.........86
2.6.3 Transaction Ordering...............................................................................87
2.6.3.1 Transaction Ordering Summary...................................................90
2.6.4 Byte Parity Checking and Generation.........................................................92
2.6.4.1 Parity Generation ......................................................................92
2.6.4.2 Parity Checking.........................................................................93
2.6.4.3 Parity Disabled..........................................................................93
2.7 ATU Error Conditions..........................................................................................94
2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface ..
95
2.7.2 Correctable Address and Correctable Attribute Errors on the PCI Interface......96
2.7.3 Uncorrectable Data Errors on the PCI Interface...........................................97
2.7.3.1 Outbound Read Request Uncorrectable Data Errors........................98
2.7.3.1.1 Immediate Data Transfer .................................................... 98
2.7.3.1.2 Split Response Termination ................................................ 99
2.7.3.2 Outbound Write Request Uncorrectable Data Errors .....................100
2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Inter-
rupts)100
2.7.3.2.2 MSI Outbound Writes........................................................ 100
2.7.3.3 Inbound Read Completions Uncorrectable Data Errors ..................101
2.7.3.4 Inbound Configuration Write Completion Message Uncorrectable Data
Errors101
2.7.3.5 Inbound Read Request Uncorrectable Data Errors ........................101
2.7.3.5.1 Immediate Data Transfer .................................................. 101
2.7.3.5.2 Split Response Termination .............................................. 101
2.7.3.6 Inbound Write Request Uncorrectable Data Errors........................101
2.7.3.7 Outbound Read Completion Uncorrectable Data Errors .................102
2.7.3.8 Outbound Split Write Uncorrectable Data Error Message ...............103
2.7.3.9 Inbound Configuration Write Request.........................................104
2.7.3.9.1 Conventional PCI Mode .................................................... 104
2.7.3.9.2 PCI-X Mode....................................................................... 105
2.7.3.10 Split Completion Messages .......................................................106
2.7.4 Correctable Data Errors on the PCI Interface ............................................107
2.7.4.1 Inbound Read Request Correctable Data Errors ...........................107
2.7.4.1.1 Immediate Data Transfer .................................................. 107
2.7.4.1.2 Split Response Termination .............................................. 107
2.7.4.2 Inbound Write Request Correctable Data Errors...........................107
2.7.4.3 Outbound Read Completion Correctable Data Errors.....................108
2.7.4.4 Inbound Configuration Write Request.........................................108
2.7.4.5 Split Completion Messages .......................................................108
2.7.5 Master Aborts on the PCI Interface..........................................................109