Intel CONTROLLERS 413808 - Manual (Page 612)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
612 Order Number: 317805-001US
10.7.21 FIQ Interrupt Source Register 0 — FINTSRC0
The FIQ Interrupt Source register 0 is a 32-bit Coprocessor 6 control register used to
specify which interrupts that are steered to the internal FIQ exception are unmasked by
the INTCTL0 register and active. The INTSTR0 control register is used to steer
individual interrupts to the FIQ exception.
The FINTSRC0 register may be used by an Interrupt Service Routine (ISR) to
determine quickly the source of an FIQ interrupt.
Table 403. FIQ Interrupt Source Register 0 — FINTSRC0 (Sheet 1 of 2)
Bit Default Description
31 0
2
XINT7# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
30: 0
2
XINT6# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
29: 0
2
XINT5# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
28: 0
2
XINT4# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
27 0
2
XINT3# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
26 0
2
XINT2# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
25 0
2
XINT1# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
24 0
2
XINT0# Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
23:19 0
2
Reserved.
18 0
2
Intel XScale ® Processor Cache Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
17 0
2
Intel XScale ® Processor PMU Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL0
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 7, Register 0