Intel CONTROLLERS 413808 - Manual (Page 529)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 529
SRAM Memory Controller—Intel
®
413808 and 413812
8.3.4.1 Parity Generation
The direct memory port interface of the SMCU only generates data parity before
delivering data onto the port. After the requested data is read from memory and ECC
has been verified, the direct memory port interface generates even data parity before
delivering the data on the direct memory port. Table 347 lists the data bytes that are
used for data parity calculation. The parity bits are calculated by bit XORing the data
bits as shown in Table 347 . As an example, the parity calculation for the lowest order
byte of the data bus D[7:0] is calculated as follows:
Note: The direct memory port does not support address parity.
Equation 15.D_PARITY0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR
D[6] XOR D[7] XOR BE[0]
Table 347. Data Parity Checking/Generation
Data Parity Bit Data Byte Byte Enable
D_PARITY15 D[127:120] BE[15]
D_PARITY14 D[119:112] BE[14]
D_PARITY13 D[111:104] BE[13]
D_PARITY12 D[103:96] BE[12]
D_PARITY11 D[95:88] BE[11]
D_PARITY10 D[87:80] BE[10]
D_PARITY9 D[79:72] BE[9]
D_PARITY8 D[71:64] BE[8]
D_PARITY7 D[63:56] BE[7]
D_PARITY6 D[55:48] BE[6]
D_PARITY5 D[47:40] BE[5]
D_PARITY4 D[39:32] BE[4]
D_PARITY3 D[31:24] BE[3]
D_PARITY2 D[23:16] BE[2]
D_PARITY1 D[15:8] BE[1]
D_PARITY0 D[7:0] BE[0]