Intel CONTROLLERS 413808 - Manual (Page 274)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
274 Order Number: 317805-001US
3.9.1.7 Poisoned TLP Received
Poisoned TLPs can be received for both Inbound Posted (Write/Message) and Inbound
Completions The two TLP types can be handled differently.
Poisoned completions are passed through to the internal bus with bad parity. In
addition to the Advanced Error requirements, the TLP header and DMA descriptor are
logged in the PCI Interface Error Log (PIE_LOGx) registers and the Intel XScale
®
microarchitecture are interrupted. When bit 4 is set in the “PCI Express Advisory Error
Control Register - PIE_AEC” , this is treated as an “Advisory Error” and an ERR_COR is
sent to the root complex; otherwise an ERR_NONFATAL is issued.
Poisoned Memory Writes are passed through to the internal bus with bad parity. In
addition to the Advanced Error requirements, the TLP header is logged in the PCI
Interface Error Log (PIE_LOGx) registers and the Intel XScale
®
microarchitecture are
interrupted. When bit 5 is set in the “PCI Express Advisory Error Control Register -
PIE_AEC” , this is treated as an “Advisory Error” and an ERR_COR is sent to the root
complex; otherwise an ERR_NONFATAL is issued.
For advisory errors, the firmware can reissue the transaction one or more (finite) times
in an attempt to get valid data. When firmware decides to stop retrying the transaction
it must escalate the error by setting the Generate ERR_NONFATAL bit in the “PCI
Express Advisory Error Control Register - PIE_AEC” .
Note: When the severity setting in “PCI Express Uncorrectable Error Severity - ERRUNC_SEV”
register is fatal this is not an Advisory Error and an ERR_FATAL is sent to the root
complex. Auto-recovery is discouraged as the ERR_FATAL message likely brings down
the hierarchy.
3.9.1.8 Completion Timeout
When an out-bound non-posted request results in a completion timeout, the Advanced
Error registers are updated and the initial request header and corresponding DMA
descriptor tag are logged in the PCI Interface Error Log (PIE_LOGx) registers and the
Intel XScale
®
microarchitecture are interrupted. When bit 6 is set in the “PCI Express
Advisory Error Control Register - PIE_AEC” , this is treated as an “Advisory Error” and
an ERR_COR is sent to the root complex; otherwise an ERR_NONFATAL is issued.
For advisory errors, the firmware can reissue the transaction one or more (finite) times
in an attempt to get valid data. When firmware decides to stop retrying the transaction
it must escalate the error by setting the Generate ERR_NONFATAL bit in the “PCI
Express Advisory Error Control Register - PIE_AEC” .
Note: When the severity setting in “PCI Express Uncorrectable Error Severity - ERRUNC_SEV”
register is fatal this is not an Advisory Error and an ERR_FATAL is sent to the root
complex. Auto-recovery is discouraged as the ERR_FATAL message likely brings down
the hierarchy.