Intel CONTROLLERS 413808 - Manual (Page 56)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
56 Order Number: 317805-001US
2.2.1.1 Inbound Address Translation
The ATU allows external PCI bus initiators to directly access the internal bus. These PCI
bus initiators can read or write 4138xx memory-mapped registers or 4138xx local
memory space. The process of inbound address translation involves two steps:
1. Address Detection.
a. Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
within the address windows defined for the inbound ATU.
b. Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
mode and with Decode A DEVSEL# timing in the PCI-X mode.
2. Address Translation.
a. Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a
36-bit 4138xx internal bus address.
The ATU uses the following registers in inbound address window 0 translation:
• Inbound ATU Base Address Register 0
• Inbound ATU Limit Register 0
• Inbound ATU Translate Value Register 0
• Inbound ATU Upper Translate Value Register 0
The ATU uses the following registers in inbound address window 1 translation:
• Inbound ATU Base Address Register 1
• Inbound ATU Limit Register 1
• Inbound ATU Translate Value Register 1
• Inbound ATU Upper Translate Value Register 1
The ATU uses the following registers in inbound address window 2 translation:
• Inbound ATU Base Address Register 2
• Inbound ATU Limit Register 2
• Inbound ATU Translate Value Register 2
• Inbound ATU Upper Translate Value Register 2
The ATU uses the following registers in inbound address window 3 translation:
• Inbound ATU Base Address Register 3
• Inbound ATU Limit Register 3
• Inbound ATU Translate Value Register 3
• Inbound ATU Upper Translate Value Register 3
Inbound address detection is determined from the 32-bit PCI address, (64-bit PCI
address during DACs) the base address register and the limit register. In the case of
DACs none of the upper 32-bits of the address is masked during address comparison.
The algorithm for detection is:
Equation 1. Inbound Address Detection
When PCI_Address [31:0] & Limit_Register[31:0] == Base_Register[31:0] and
PCI_Address [63:32] == Base_Register[63:32] (for DACs only) the PCI Address is claimed by the Inbound
ATU.