Intel, Bit default description – Intel CONTROLLERS 413808 User Manual

Page 220

Intel

413808 and 413812—Address Translation Unit (PCI-X)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

220

Order Number: 317805-001US

2.14.82 PCI Interface Error Control and Status Register - PIECSR

This register indicates whether or not the ATU has detected and logged a PCI interface

error. The register is also used to enabled the logging of additional errors. For more

details, see

Section 2.7, “ATU Error Conditions” on page 94

Note:

The

“PCI Interface Error Control and Status Register - PIECSR”

“PCI Interface Error

Address Register - PCIEAR”

, and

“PCI Interface Error Upper Address Register -

PCIEUAR”

report the original transaction when an error is detected on the current

transaction. For example, when the Split Completion of an original Outbound Read

request had an error, the information regarding the Outbound Read is reported.

Table 109. PCI Interface Error Control and Status Register - PIECSR

Bit

Default

Description

31:17 0000 0000H Reserved

16:13

Error Command - This field indicates the PCI command when PCIECSR bit 0 is set:

This field represents the command type used during the PCI transaction other than the DAC command

(when Dual Address Cycle).

The 4-bit code in this field can be referenced to the actual command type via Table 2-8, “PCI-X

Command Encoding” of the PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0.

12:09

0000

Error Type - This field indicates the type of PCI interface error when PCIECSR bit 0 is set:

0000 Address Parity Error

0001 Data Parity Error

0010 Master Abort

0011 Target Abort

0100 Received Split Completion Error Message

0101 Unexpected Split Completion

0110 Split Completion Discarded

0111 Internal Bus Data Parity Error

08:05

0000

Initiator ID - When PCIECSR bit 0 is set, this Indicates the initiator associated with the detected PCI

interface error.

“0000” is used to denote inbound requests where the IOP was the completer of the transaction.

See Internal Bus Requester IDs in the System Controller chapter for remaining details of Initiator ID.

04:02

000

PCI Function Number - When PCIECSR bit 0 is set, this field indicates the device function number that

this error is associated with.

Note:

This field is undefined when the Error Type (bits 12:09) indicates an Address Parity Error.

Multiple PCI Interface Errors Detected - This bit is set when a PCI Interface Error has already been

logged (bit 0 of the PIECSR is set), but an additional error is detected. Note that a second error is logged

for a subsequent transaction.

PCI Interface Error Detected - This is bit is set when a PCI Interface Error is detected. When this register

is cleared, the 4138xx is enabled to latch information about a PCI Interface error.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

+380H